When a compliance test fails, such as with IEC61000-4-2, the designer may receive scant information about how to proceed.
All that is known is that the system failed in a particular manner, with a particular stress applied to a general area.
A combination of Susceptibility Scanning and Current Reconstruction can be used to track the transient entry vector, how it spreads through the system, and which vulnerable hotspots are reached by it.
From this, iterative improvements can be validated quantitatively and the margin gained can be assessed.
This methodology can be used in conjunction with high level simulations to minimize the testing iterations, and to try out PCB re-routing ideas or new component revisions, for example, that would be cost- or time-prohibitive from a pure trial and error approach.